Different from a normal random access memory (RAM) that can be randomly read, erased and programmed on a byte basis, a conventional EPROM-type flash memory features a byte-program and a block-erase capability with each block containing a number of bytes. Because the data within a memory block can not be selected for erasure individually, a flash memory has to erase the data of a whole block of memory cells, i.e., an erase block, and then program the new data byte by byte.
As is well known, erasing a block of cells may cause a serious problem that the cells having faster erasing speed may be over-erased. The threshold voltage Vt of an over-erased cell becomes negative and consequently can not be shut off by the ground voltage which is generally applied to the gates of non-selected cells in a read operation. In a standard NOR architecture array, the over-erased cells conduct leakage current and cause errors in the read operation. To solve this problem, the Vt's of over-erased cells are typically programmed back to positive by a repair operation.
Various bias conditions have been described in prior arts for the repair operation, but they all suffer different drawbacks. Among the repair approaches developed in the industry during the past years, the most distinguished ones may be those using the mechanism of hot-electron injection. Because hot-electron injection has the advantage that the final Vt of the cell can be better controlled after the repair operation, it has been preferred over other mechanisms such as Fowler-Nordheim tunneling.
In the mechanism of hot-electron injection, the Vt of the cell is increased by hot-electron injection induced by the channel current. The Vt of the cell automatically saturates at a final Vt when it is sufficiently high to turn the channel current off. Therefore, the cell will not be over-repaired too much. The distribution of the Vt's of a large number of cells after repair can be easily controlled within a tight region.
U.S. Pat. No. 5,521,867 probably represents the most famous prior art that discloses the repair operation using hot-electron injection. The bias condition of the repair approach is shown in FIG. 1. The drain is applied with a voltage around +6.5V and both the gate and the source are grounded. This bias condition is almost identical to the conventional bias condition for programming using channel hot-electron except that the gate voltage is +8V in a programming operation.
The reason of using a ground voltage 0V as the gate voltage is that the final Vt is desired to be around +1V. At the beginning, the Vt of an over-erased cell is lower than 0V that causes large channel current to conduct and hot-electron injection to occur. The Vt of the cell is gradually increased until it reaches a value close to +1V which turns off the channel current. Therefore, no sufficient current continues to generate hot-electron and the final Vt of the cell saturates at around +1V after repairing.
This prior art successfully repairs the Vt of an over-erased cell to +1V. However, there are a number of drawbacks in this conventional repairing approach. One drawback is that it requires large drain current such as 500 uA per cell during the repair operation. The large current makes it difficult to provide the drain voltage from an on-chip charge pump circuit. In addition, to get the +6.5V drain voltage it is often necessary that the power supply voltage be pumped up by the charge pump circuit because the power supply voltage of the industry standard today is moving toward +3V. It is especially true for a handheld equipment.
Furthermore, the supply current of the charge pump circuit limits the number of memory cells that can be repaired in parallel. As described in the prior art, it is suggested that the repair operation be performed byte by byte rather than a bit line or a block at one time because the charge pump circuits can not afford the large repairing current. Otherwise, the pump circuits may be overloaded and the repair operation will fail.
However, byte by byte repairing prolongs the total repair time to several orders of the time for repairing one byte. On the other hand, simply lowering the supply current of the drain can also result in drastically long time needed to repair the cells. Therefore, the very long repair time is another drawback associated with the conventional repair approach. Using the conventional bias condition for repairing, the repair time is approximately 100 ms for repairing a single cell. It can take up to several seconds to repair all the over-erased cells in the array. This long repair time is usually considered part of the time of an erase operation. The erase time is consequently long and the yield of a repair operation is reduced.
Recently, substrate bias condition of a flash memory cell has attracted wide industrial interest. By having a negative substrate voltage, the drain voltage can be lowered while still maintaining constant drain to bulk voltage V.sub.DB. Therefore, it significantly reduces the supply current requirement of the drain pump circuits without sacrificing the repair efficiency as compared to the conventional repair approach. This is advantageous especially when the pump circuit is needed in order to work under low power supply environment, such as +3V.
An early development of the approach involving substrate bias is described in a published paper entitled "Substrate-Current-Induced Hot Electron (SCIHE) Injection: A New Convergence Scheme for Flash Memory", IEEE Tech. Dig. IEDM 1995, pp. 283-286. Referring to FIG. 2 for the bias condition of this approach. The cell is applied with a negative substrate voltage, -3V, and the drain voltage is reduced from the conventional +6.5V to +4.5V only.
As can be seen, this repair condition reduces the required drain voltage by 2V, thus reducing the loading of the charge pump circuit. As is well known, the supply current of a charge pump circuit has a strong reverse-ratio to the pump's output voltage. Therefore, the repairing yield can be improved and the required area of the pump circuits can be reduced. Note that the gate voltage is applied with +1.4V and the final Vt of the cell is measured around 1V.
However, this approach still can not solve the long repair time problem associated with the repair operations that rely on hot-electron injection. The paper shows that the repair time is 100 us per cell when the drain voltage is applied with +4.5V. A person skilled in the art should understand that if +3.3V power supply is applied to the drain, the repairing time will be dramatically prolonged to at least two orders. To make a fair comparison in the later part of this specification, a +3.3V will be used as the drain voltage for this art in the rest of this document.
Another prior art in a published paper entitled "Secondary Electron Flash--a High Performance, Low Power Flash Technology for 0.35 um and Below", IEEE Tech. Dig. IEDM 1997, pp. 279-282, describes a bias condition as shown in FIG. 3. The gate is applied with +3V to +5V rather than +1.4V as in the previously described prior art. By increasing the gate voltage, it generates stronger vertical electric field for increasing the hot-electron injection into the floating gate. The programming time is dramatically shortened from several mini seconds to 10 us range.
However, this approach can only be applied to a programming operation to enhance the conventional channel hot-electron programming rather than a repair operation. The limitation is due to the fact that the Vt of the cell saturates at a much higher voltage because of the higher gate voltage. As shown in the paper, if the gate voltage is applied with +3V, the final Vt of the cell does not saturate until it reaches +2.5V. If the gate voltage is applied with +5V, the cells' Vt does not saturate until +4.2V. This high final Vt is not acceptable for a repair operation because it requires mush lower final Vt, such as +1V, to have reasonable current in a read operation.
As a result, both prior art approaches using negative substrate voltage have their own problems. For the low gate voltage approach, the repair efficiency is low. For the high gate voltage approach, the high final Vt prevents it from being used for a repair operation.